A Ternary Content Addressable Search Engine

This paperdeseribes the design, implementation, and experimental results for a ternary content addressable search engine cfdp, known as the Database Accelerator (DBA). The DBA chip architecture is presented, and it is well suited to serve as a coprocessor for a variety of logical search applications. The core of the DBA system is composed of novel high-density content addressable memory (CAM) cells capable of storing three states. The design of these cells and their support circuitry is described. The CAM cell and support circuitry were fabricated and their operation confirmed. The circuit implementation of the DBA data path is described with particular emphasis on the optimization of the multiple response resolver. The timing and control methodology, which simultaneously satisfies the complexity, speed, and robustness requirements of the DBA chip, is reported. Fhally, experimental DBA chip results are presente@ these results verify the full functionality and testability of the design.